1. Field of the Invention
This invention relates to the formation of contacts for integrated circuit structures. More particularly, this invention relates to an improved process for forming self-aligned metal silicide contacts for MOS structures at lower temperatures to conserve thermal budget while minimizing device degradation.
2. Description of the Related Art
In the formation of contacts to the source and drain regions and gate electrode of an MOS integrated circuit device, it has become an established practice to enhance the conductivity of the contacts by reacting the exposed doped silicon surfaces of the source and drain regions and the doped silicon gate electrode with a metal such as titanium capable of forming a metal silicide which will have a lower resistivity than the doped silicon itself. One conventional way of forming such metal silicide contacts is to blanket deposit over the integrated circuit structure (including the SiO.sub.2 insulation material adjacent the exposed silicon regions) a layer of a metal, such as titanium, capable of reacting with the silicon to form the desired metal silicide contact material. Following the blanket deposit, the structure is annealed at an elevated temperature sufficiently high so that the metal will react with the exposed silicon to form the desired metal silicide. Usually this anneal is carried out in a nitrogen atmosphere to both inhibit the undesirable formation of metal oxide and to form metal nitride which is beneficial for adherence of a metal layer subsequently formed over the metal silicide layer.
It has been found, however, that the temperature must be carefully controlled during this anneal to avoid the simultaneous undesirable reaction of the silicide-forming metal layer with the silicon in the silicon oxide insulation material adjacent the exposed silicon. For example, when using titanium as the silicide-forming metal, the temperature of the anneal should be about 600-700.degree. C. to avoid reaction between the titanium and the silicon in the silicon oxide insulation to avoid degradation of the insulation or the formation of undesired titanium silicide over the insulation. However, this results in the formation of a metal silicide over the exposed silicon having a phase (C49) which is less than satisfactory as a conductive contact material. To overcome this, the structure is etched to remove unreacted metal, e.g., titanium, and then the structure is subject to a second, higher temperature, anneal of about 800.degree. C., which will convert the already formed metal silicide, e.g., titanium silicide, to a phase (C54) which is more desirable for use as an electrically conductive metal silicide contact, without risk of reacting titanium metal with the silicon oxide insulation at this higher annealing temperature, since the unreacted metal, e.g., titanium, has already been removed by the etch step prior to the exposure of the structure to the higher annealing temperature.
While the above two step annealing process has been satisfactory for larger line width structures, as the line widths shrank in size, the time and temperature required to convert the C49 phase titanium silicide to the more desirable C54 phase has increased, apparently due to a reduction in nucleation sites in the titanium silicide. This, in turn, is the result of the large grain sizes of the titanium silicide relative to the size of the line widths wherein the normal two dimensional density of grain boundaries (and therefore density of nucleation sites) has been reduced to one dimension as the line width dimension approaches the same size as the grain.
To overcome this problem, it has been proposed to decrease the grain size of the metal silicide which would, in turn, increase the grain boundaries and therefore increase the nucleation sites. Horiuchi et al., in an article entitled "A New Titanium Salicide Process (DIET) for Sub-quarter Micron CMOS", describe the use of pre-amorphization of the silicon prior to the silicide formation, which results in the subsequent formation of smaller grain C49-TiSi.sub.2 during the siliciding step, thereby increasing the density of nucleation sites. This, then, means that smaller line width structures could have the same thermal budgets as larger line width structures, from the standpoint of C54 phase TiSi.sub.2 formation.
This local amorphization of the silicon substrate adjacent the surface of the substrate, and the polysilicon gate electrode adjacent its surface, is carried out by the blanket implantation of the silicon surfaces, for example, with arsenic. Such conventionally amorphization is usually carried out using a tilt angle of from 0-10.degree. between the axis of the implant beam and a line perpendicular to the plane of the surface of the substrate when a silicon substrate having a 100 crystallographic surface orientation is implanted. A 100 oriented surface silicon substrate is the preferred crystallographic orientation for the formation of MOS devices in/on a silicon substrate.
However, it has been discovered that the leakage of small line width NMOS structure increases when using such amorphization of the silicon. Apparently this is due to penetration (into the NMOS channel) of some of the implanted amorphizing ions which pass completely through the polysilicon gate electrode which is supposed to act as a mask for the underlying channel region of the substrate. Apparently this passage of the implanting ions through the gate electrode is made possible because as the line widths shrink, so does the thickness of the gate electrode, thereby resulting in a thinner polysilicon gate electrode which more easily penetrated by the implanting ions than previous thicker gate electrodes utilized with larger line-width technologies. This penetration of the implanting ions through the thin polysilicon gate electrode is believed to be exacerbated by the presence of some crystalline grains of silicon in the polysilicon which not only extend from the top surface of the electrode to the bottom surface (because of the thinness of the polysilicon electrode), but are also oriented crystallographically in such a way that the implanted ion can channel through the polysilicon crystal into the underlying MOS channel in the substrate. That is, the implanted ion sees the particular crystalline grain as a single crystal structure oriented to permit the implanted ion to channel through the crystal.
It would, therefore, be desirable to provide a smaller grain size metal silicide by amorphizing of the silicon, to thereby enhance the subsequent higher temperature anneal of the metal silicide while conserving the thermal budget, without, however, degrading the performance of the MOS devices in the integrated circuit structure.